1. Field of the Invention
The present invention is related to a fractional arithmetic unit, a fractional arithmetic method, a set-up engine for handling graphic images implemented with the fractional arithmetic unit in the field of the 3D graphics technique, and a computer-readable medium for using the fractional arithmetic method.
2. Description of the Related Art
FIG. 1 is a schematic diagram showing a typical 3D graphics system for drawing triangles, rectangles, lines and so forth as known in the field of 3D computer graphics.
As illustrated in the same figure, the 3D graphics system is composed of a set-up engine 91 and a rasterizer 92. The set-up engine 91 serves to receive information IN about vertices of each of draw primitives such as triangles, rectangles, lines and so forth, calculate parameters required for generating pixel data and output the parameters to a pixel generator of the rasterizer 92.
The rasterizer 92 serves to generate the pixel data and perform the operation of the respective pixels. The result of the operation is stored in a VRAM 95 comprising a frame buffer and a Z buffer and drawn in the screen of a monitor not shown in the figure.
The pixel generator of the rasterizer 92 as described above has to be designed to calculate color values of (R,G and B, i.e., red, green and blue), xcex1 values(A), fog coefficients (F), texture coordinates (STRQ), and depth values (Z), usually by the sequentially accumulative addition (DDA; Digital Differential Analyzer).
The sequentially accumulative addition is performed by obtaining the differential value between the property values after and before unit pixel shift for each property. The necessary operation is performed by the set-up engine 91.
In the case that a triangle is rasterized as a draw primitive, the differential value as described above is calculated by the following plane equation (1) in general.
∂p/∂x={(p2xe2x88x92p0)(y1xe2x88x92y0)xe2x88x92(p0xe2x88x92p1)(y0xe2x88x92y2)}e0xe2x80x83xe2x80x83(1)
In the above plane equation (1), p0, p1 and p2 are the property values of the respective vertices; e0 is twice the area of the triangle; and ∂P/∂x is the gradient in the X-direction.
The conventional set-up engine 91 as illustrated in FIG. 1 is composed in general of a fractional arithmetic unit including a denominator calculation unit 101, a numerator calculation unit 102 and a division unit 103 as illustrated in FIG. 2.
Two operations are required for each property value in the set-up engine 91 in the X-direction and in the Y-direction. Also, for each of the two operations, required calculations are two multiply operations as performed by the denominator calculation unit 101, additional two multiply operations as performed by the numerator calculation unit 102, and one division operation as performed by the division unit 103.
Usually, in the case of the 3D graphics system, there are a number of the property values as described above to be processed respectively by several operations as described above.
However, there are following shortcomings (1) and (2) in the conventional 3D graphics system as described above.
(1) The operations as described above places heavy burden on the set-up engine so that it is required for improving the operational speed to provide much hardware resources. Particularly, the primary problem is the division operation which has to be repeatedly performed. In the case that an integer arithmetic unit (fixed point arithmetic unit), the division operation has to be performed for the respective calculation. In the case of the prior art fractional arithmetic unit as illustrated in FIG. 2, a plurality of the division units 103 have to be arranged in parallel for the purpose of improving the processing speed.
(2) Furthermore, taking the precision of arithmetic operations into consideration, it is understood that there are many calculations which are roughly performed as fixed point arithmetic operations. In this case, while certain property values are represented with a fixed bit length (referred to as the integer bit hereinbelow), internal arithmetic operations (accumulative operations) have to be performed also with lower bits (referred to as fractional bits hereinbelow). The bit length of the fractional bits is determined by the accumulation times (i.e., maximum shift). For example, in the case that the X,Y space is 212xc3x97212, there are 15 to 16 fractional bits as required. Because of this, high precision arithmetic operations are required to the set-up engine, and then a large number of clocks are consumed by the high precision arithmetic operations.
In this manner, the set-up engine is implemented with much hardware resources, and is operated with a number of clocks to complete arithmetic operations taking a much processing time.
The present invention has been made in order to solve the shortcomings as described above. It is an object of the present invention to provide a fractional arithmetic unit capable of high speed operations with a small scale hardware, a fractional arithmetic method, a set-up engine for handling graphic images implemented with the fractional arithmetic unit in the field of the 3D graphics technique, and a computer-readable medium for using the fractional arithmetic method.
It is another object of the present invention to provide an improved fractional arithmetic unit, a fractional arithmetic method, a set-up engine for handling graphic images implemented with the fractional arithmetic unit in the field of the 3D graphics technique, and a computer-readable medium for using the fractional arithmetic method, in which the performance of the 3D graphics engine is adjusted depending upon the areas of the draw primitive.
In brief, the above and other objects and advantages of the present invention are provided by a new and improved fractional arithmetic unit comprising: a reciprocal number arithmetic logic unit; and a multiply arithmetic circuit for multiplying the numerator and the reciprocal number of a denominator as obtained by said reciprocal number arithmetic logic unit, wherein the precision of the calculation performed by said reciprocal number arithmetic logic unit is controlled in accordance with the precision as required for a fractional arithmetic operation; and wherein said multiply arithmetic circuit outputs the result of multiplication as the result of said fractional arithmetic operation.
Also, in accordance with a preferred embodiment of the present invention, said reciprocal number arithmetic logic unit is composed of a reciprocal number arithmetic logic circuit which serves to improves the precision of calculation by repeating the reciprocal number arithmetic operation.
Furthermore, in accordance with a preferred embodiment of the present invention, said reciprocal number arithmetic logic unit is composed of the reciprocal number arithmetic logic circuit which serves to perform floating point arithmetic operations.
In accordance with another aspect of the present invention, a fractional arithmetic unit comprises: a denominator calculation unit for calculating a denominator from an input value: a numerator calculation unit for calculating a numerator from said input value; a floating point conversion unit for converting the output of said denominator calculation unit to a floating point value; a reciprocal number calculation unit for performing the reciprocal number arithmetic operation for obtaining the reciprocal number of the output of said floating point conversion unit on the basis of a repetition technique for improving the precision of calculation by repeating the operation; and a multiply arithmetic circuit for multiplying the output of said reciprocal number calculation unit and the output of said numerator calculation unit, wherein said multiply arithmetic circuit is composed of an arithmetic precision judgment unit for judging whether or not the output of said reciprocal number calculation unit reaches a precision as required for a fractional arithmetic operation; wherein if said arithmetic precision judgment unit makes a judgment as not reaching the sufficient precision as required, said reciprocal number calculation unit continues repeating the reciprocal number arithmetic operation until the output of said reciprocal number calculation unit reaches the sufficient precision as required; and wherein when the sufficient precision as required is reached, said multiply arithmetic unit 65 initiates the multiply arithmetic operation and outputs the result of multiplication as the output of said fractional arithmetic operation.
Furthermore, in accordance with a preferred embodiment of the present invention, if said arithmetic precision judgment unit judges that the precision of calculation as required is reached, the multiply arithmetic operation by said multiply arithmetic circuit is immediately initiated without further repetition.
In accordance with a further aspect of the present invention, a set-up engine for handling graphic images comprises the fractional arithmetic unit as described above, wherein the fractional arithmetic operation as performed by said fractional arithmetic unit is to calculate the gradient value of property values as assigned respectively to the pixels constituting draw primitives in the X-direction and in the Y-direction.
In accordance with a further aspect of the present invention, a fractional arithmetic method is implemented with a fractional arithmetic unit comprising: a denominator calculation unit for calculating a denominator from an input value; a numerator calculation unit for calculating a numerator from said input value; a floating point conversion unit for converting the output of said denominator calculation unit to a floating point value; a reciprocal number calculation unit for performing the reciprocal number arithmetic operation for obtaining the reciprocal number of the output of said floating point conversion unit on the basis of a repetition technique for improving the precision of calculation by repeating the operation; and a multiply arithmetic circuit for multiplying the output of said reciprocal number calculation unit and the output of said numerator calculation unit.
The fractional arithmetic method is used for subsequently performing fractional arithmetic operations from an operation thereof having a lower precision as required to an operation thereof having a higher precision as required in which, while a common denominator is used for said fractional arithmetic operations, the numerator of each fractional arithmetic operation is calculated anew by the fractional arithmetic unit.
In this case, each fractional arithmetic operation is performed by a step of calculating by calculating said denominator from said input value by means of said denominator calculation unit; a step of for calculating said numerator from said input value by means of said numerator calculation unit; a step of for converting the result of the calculation from said denominator calculating step to a floating point value by means of said floating point conversion unit; a step of calculating the reciprocal number of said denominator as converted by said floating point conversion step by means of said reciprocal number calculation unit; a step of judging whether or not the output of said reciprocal number calculation unit has a sufficient precision as required for each of a plurality of said fractional arithmetic operations for the purpose of achieving said precision as required which has been predetermined; a step of repeating the operation by said reciprocal number calculation unit, if the sufficient precision as required is judged as not reached on the basis of the result of said judging step, until the sufficient precision as required of the reciprocal number output from said reciprocal number calculation unit is reached; and a step of outputting the result of the fractional arithmetic operation by multiplying the result of the numerator calculation and the result of said reciprocal number calculation by means of said multiply arithmetic circuit after the sufficient precision as required of the reciprocal number output from said reciprocal number calculation unit is reached.
Furthermore, in accordance with a preferred embodiment of the present invention, when the output of said reciprocal number calculation unit reaches the sufficient precision as required, said outputting step is immediately initiated without repeating the operation.
In accordance with a further aspect of the present invention, a fractional arithmetic method is implemented with a fractional arithmetic unit comprising: a denominator calculation unit for calculating a denominator from an input value; a numerator calculation unit for calculating a numerator from said input value; a floating point conversion unit for converting the output of said denominator calculation unit to a floating point value; a reciprocal number calculation unit for performing the reciprocal number arithmetic operation for obtaining the reciprocal number of the output of said floating point conversion unit on the basis of a repetition technique for improving the precision of calculation by repeating the operation; and a precision obtaining unit for obtaining the precision as required of the fractional arithmetic operation by said reciprocal number calculation unit from said input value; and a multiply arithmetic circuit for multiplying the output of said reciprocal number calculation unit and the output of said numerator calculation unit.
The multiply arithmetic circuit is then composed of an arithmetic precision judgment unit for judging whether or not the output of said reciprocal number calculation unit reaches the precision as required which has been obtained by said precision obtaining unit.
Furthermore, if said arithmetic precision judgment unit makes a judgment as not reaching the sufficient precision as required, said reciprocal number calculation unit continues repeating the reciprocal number arithmetic operation until the output of said reciprocal number calculation unit reaches the sufficient precision as required; and when the sufficient precision as required is reached, said multiply arithmetic unit initiates the multiply arithmetic operation and outputs the result of multiplication as the output of said fractional arithmetic operation.
Furthermore, in accordance with a preferred embodiment of the present invention, if said arithmetic precision judgment unit judges that the precision of calculation as required is reached, the multiply arithmetic operation by said multiply arithmetic circuit is immediately initiated without further repetition.
Furthermore, in accordance with a preferred embodiment of the present invention, the fractional arithmetic operation as performed by said fractional arithmetic unit is to calculate the gradient value of property values as assigned respectively to the pixels constituting draw primitives in the X-direction and in the Y-direction.
Furthermore, in accordance with a preferred embodiment of the present invention, the fractional arithmetic operation as performed by said fractional arithmetic unit is to calculate the gradient value of property values as assigned respectively to the pixels constituting draw primitives in the X-direction and in the Y-direction.
In accordance with a further aspect of the present invention, a fractional arithmetic method is implemented with a fractional arithmetic unit comprising: a denominator calculation unit for calculating a denominator from an input value; a numerator calculation unit for calculating a numerator from said input value; a floating point conversion unit for converting the output of said denominator calculation unit to a floating point value; a reciprocal number calculation unit for performing the reciprocal number arithmetic operation for obtaining the reciprocal number of the output of said floating point conversion unit on the basis of a repetition technique for improving the precision of calculation by repeating the operation; and a multiply arithmetic circuit for multiplying the output of said reciprocal number calculation unit and the output of said numerator calculation unit.
The fractional arithmetic method is used for subsequently performing fractional arithmetic operations from an operation thereof having a lower precision as required to an operation thereof having a higher precision as required in which, while a common denominator is used for said fractional arithmetic operations, the numerator of each fractional arithmetic operation is calculated anew by the fractional arithmetic unit.
In this case, each fractional arithmetic operation is performed by:
a step of calculating by calculating said denominator from said input value by means of said denominator calculation unit; a step of for calculating said numerator from said input value by means of said numerator calculation unit; a step of for converting the result of the calculation from said denominator calculating step to a floating point value by means of said floating point conversion unit; a step of calculating the reciprocal number of said denominator as converted by said floating point conversion step by means of said reciprocal number calculation unit; a step of obtaining the precision as required of the fractional arithmetic operation by said reciprocal number calculation unit from said input value; a step of judging whether or not the output of said reciprocal number calculation unit reaches the precision as required which has been obtained by said precision obtaining step; wherein a step of repeating the operation by said reciprocal number calculation unit, if the sufficient precision as required is judged as not reached on the basis of the result of said judging step, until the sufficient precision as required of the reciprocal number output from said reciprocal number calculation unit is reached; and a step of outputting the result of the fractional arithmetic operation by multiplying the result of the numerator calculation and the result of said reciprocal number calculation by means of said multiply arithmetic circuit after the sufficient precision as required of the reciprocal number output from said reciprocal number calculation unit is reached.
Furthermore, in accordance with a preferred embodiment of the present invention, when the output of said reciprocal number calculation unit reaches the sufficient precision as required, said outputting step is immediately initiated without repeating the operation.
Furthermore, in accordance with a preferred embodiment of the present invention, a computer-readable medium is embodied a computer program for performing the respective steps of the fractional arithmetic method as described above.